1. Field of the Invention
The present invention relates to a delay circuit device, and more specifically to a delay circuit used in transmission and generation of a synchronizing signal, namely, a clock signal in a semiconductor device.
2. Description of Related Art
Recently, a system installed on a semiconductor device has been remarkably speeded up, with the result that a time difference between a clock supplied to the semiconductor device from an external device and a clock generated internally in the semiconductor device on the basis of the externally supplied clock becomes non-negligible. As a countermeasure for this, for example, a phase locked loop (called a "PLL" hereinafter) has been used in the prior art. FIG. 6 illustrate a fundamental construction of the PLL circuit.
A phase comparator 601 outputs a phase difference signal 606 based on a phase difference between an external clock 603 supplied through a receiver circuit 602 and an internal clock 605 supplied through a delay circuit 604 having a delay equivalent to that of the receiver circuit 602. The phase difference signal 606 is supplied through a loop filter 607 as a control signal 608 to a voltage controlled oscillator (VCO) 609. This voltage controlled oscillator 609 generates a clock 610 having the frequency in accordance with the control signal 608. The clock signal 610 is amplified by an amplifier circuit 611 to become the internal clock 605 which is used in a clock-controlled circuit 612. The control signal 608 controls the voltage controlled oscillator 609 to make the phase difference between the external clock 603 and the internal clock 605 zero, and controls the voltage controlled oscillator 609 until the phase difference can no longer be detected finally.
Therefore, in the PLL circuit, a delay between the external clock and the internal clock becomes zero, with the result that it is possible to avoid a problem that a delay time becomes relatively large in comparison with the period of the clock and therefore a trouble occurs in a circuit operation.
As a means for solving the problem of a circuit using the PLL circuit, Japanese Patent Application No. 316875/1994 (Japanese Patent Application Pre-examination Publication No. JP-A-08-237091) proposes a delay circuit device as shown in FIG. 7.
Referring to FIG. 7, it comprises a delay circuit array 701 so constructed that an output can be taken out from an arbitrary position of a signal transmission path, a delay circuit array 702 so constructed that an input can be applied to an arbitrary position of a signal transmission path, a control circuit 703 having a signal input terminal and a signal output terminal, a load adjusting device 704 for equalizing a load of the delay circuit array 701 and a load of the delay circuit array 702, a receiver circuit 705 receiving an external signal, an amplifier circuit 706, a delay circuit 707 having a delay time equivalent to that of the receiver circuit 705, and a delay circuit 708 having a delay time equivalent to that of the amplifier circuit 706.
An output of the receiver circuit 705 is connected to an input of the delay circuit 707 and the control circuit 703. An output of the delay circuit 707 is connected to an input of the delay circuit 708. An output of the delay circuit 708 is connected to an input of tile delay circuit array 701. An output of the delay circuit array 702 is connected to an input of the amplifier circuit 706. The delay circuits 707 and 708 have the delay times equivalent to those of the receiver circuit 705 and the amplifier circuit 706, respectively, in order to make an input clock 801 and an output timing of an output clock 805 coincident with each other.
Here, internal structures of the delay circuit array 701, the delay circuit array 702, the control circuit 703 and the load adjusting device 704 will be described. The delay circuit array 701 and the delay circuit array 702 are constructed of inverters and NAND gates which are alternately located, and the control circuit 703 and the load adjusting device 704 are constructed of NAND gates.
The delay circuit 701 includes a NAND gate FN1, an inverter FI1, a NAND gate FN2, an inverter FI2, . . . , a NAND gate FNn, an inverter FIn, a NAND gate FNn+1, an inverter FIn+1, . . . , which are located in the named order from an input side.
The delay circuit 702 includes an inverter RI1, a NAND gate RN1, an inverter RI2, a NAND gate RN2, . . . , an inverter RIn, a NAND gate RNn, an inverter RIn+1, a NAND gate RNn+1, . . . , which are located in the named order from an output side.
The control circuit 703 is constituted of a NAND circuit array composed of a NAND gate CN1, a NAND gate CN2, . . . , a NAND gate CNn, a NAND gate CNn+1, which have one input connected to the output of the receiver circuit 705.
The load adjusting device 704 is constituted of a NAND circuit array composed of a NAND gate GN1, a NAND gate GN2, . . . , a NAND gate GNn, a NAND gate GNn+1, which have one input connected to a ground line 710.
In addition, the delay circuit array 701, the delay circuit array 702, the control circuit 703 and the load adjusting device 704 are mutually connected. An output of the inverter Fin in the delay circuit array 701 is connected to an input of the NAND gate FNn+1 and one input of the two-input NAND gate CNn, in the control circuit 703, which is not connected to the output of the receiver circuit 705.
An output of the NAND gate CNn in the control circuit 703 is connected to one input of the two-input NAND gate FNn+2, in the delay circuit array 701, which is not connected to the output of the inverter FIn+1, and one input of the two-input NAND gate RNn, in the delay circuit array 702, which is not connected to the output of the inverter RIn+1.
An output of the NAND gate RNn in the delay circuit array 702 is connected to an input of the inverter RIn in the delay circuit array 702. An output of the inverter RIn in the delay circuit array 702 is connected to an input of the NAND gate RNn-I and one input of the two-input NAND gate GNn, in the load adjusting device 704, which is not connected to the ground.
An output of the NAND gate GNn in the load adjusting device 704 is not connected to any one.
One input of the two-input NAND gate FN1, in the delay circuit array 701, which is not connected to an input of the delay circuit array 701, one input of the two-input NAND gate FN2 which is not connected to an output of the inverter FI1, and one input of the last NAND gate in the delay circuit array 702, which is not connected to an output of the last NAND gate in the control circuit 703, are connected to a power supply line 709.
Now, an operation of this delay circuit is illustrated in an input/output timing waveform diagram of FIG. 8.
The input clock 801 is a H (high level) pulse having a constant period, a rising edge of which is used.
A clock group 802 indicates clocks which are outputted from all the inverters in the delay circuit array 701 and which therefore travel in the delay circuit array 701.
A clock 803 is a clock outputted from the receiver circuit 705 and inputted to the control circuit 703.
The receiver circuit 705 internally includes a circuit for making the width of the clock pulse to a constant width, so that the width of the clock 803 is made smaller than the width of the clock 801.
A clock group 804 indicates clocks which are outputted from all the inverters in the delay circuit array 702 and which therefore travel in the delay circuit array 702.
A clock 805 is an output of the amplifier circuit 806.
Since the clock is applied periodically, it is not necessary to distinguish the clocks from each other in an actual use, Here, however, in order to make it easy to understand the operation, the clocks are numbered as follows:
an arbitrary clock is called a (m)th clock; PA1 a next clock is called a (m+1)th clock; and PA1 a clock after the next clock is called a (m+2)th clock.
The (m)th clock is supplied from the receiver Circuit 705 through the delay circuit 707 having the delay time equivalent to that of the receiver circuit 705, and then through the delay circuit 708 having the delay time equivalent to that of the amplifier circuit 706, to the delay circuit array 701, and travels in the delay circuit array 701 and expressed by the (m)th clock group in the clock group 802.
The output of the inverters in the delay circuit array 701 is brought to the high level in response to the traveling of the (m)th clock, and is maintained at a high level during a period of the pulse width of the (m)th clock.
After one clock period after the (m)th clock is outputted from the receiver circuit 705, the (m+1)th clock is supplied from the receiver circuit 705 to the control circuit 703, and is expressed as the (m+1)th clock of the clock 803.
At this time, the (m)th clock is traveling in the delay circuit array 701. For example, assuming that the (m)th clock is traveling through an inverter group starting from a (j)th inverter FIj (an inverter positioned at a leading edge of the high level pulse) in the delay circuit array 701 and terminating at a (j-k)th inverter FIj-k (an inverter positioned at a tail edge of the high level pulse), with the width of the (m)th clock, the outputs of the (j)th inverter FIj to the (j-k)th inverter are at the high level as mentioned above.
Accordingly, the NAND gates CNj to CNj-k in the control circuit 703 connected to the inverters FIj to FIj-k through which the (m)th clock is traveling, have both the two inputs at the high level. Therefore, in the two-input NAND gates RNj to RNj-k in the delay circuit array 702 connected to the NAND gates CNj to CNj-k in the control circuit 703, one of the two inputs is brought to the low level, and therefore, the output is brought from the high level to the low level, so that the (m)th clock is traveling the delay circuit array 702 in the form of a low level pulse, which is indicated by the (m)th clock group in the clock group 804.
Furthermore, the input of the two-input NAND gates FNj+2 to FNj-k+2 in the delay circuit array 701, connected to the NAND gates CNj to CNj-k in the control circuit 703, is brought to the low level, with the result that the output of all of the inverters FIj+2 to FIj-k+2 are brought to the low level, and the (m)th clock in the delay circuit array 701 is brought to the low level.
The (m)th clock outputted from the delay circuit array 702 is outputted through the amplifier circuit 706, and is expressed as the (m)th clock in the clock 805.
Here, the respective delay times of the receiver circuit 705 and the delay circuit 707, which are equal to each other as mentioned above, is expressed as "d1", and the respective delay times of the amplifier circuit 706 and the delay circuit 708, which are equal to each other as mentioned above, is expressed as !"d2". In addition, the period of the clock is expressed as "tck". A delay from the rising edge of the (m)th clock of the input clock 801 to the rising edge of the (m)th clock of the output clock 803 of the receiver circuit 705 is "d1".
A delay from the (m)th clock of the output clock 803 of the receiver circuit 705 to the rising edge of a heading clock of the (m)th clock group in the clock group 802 traveling in the delay circuit array 701, is equal to the delay from the (m)th clock of the output clock 803 of the receiver circuit 705 to the (m+1)th clock of the output clock 803 of the receiver circuit 705, and is "tck".
Accordingly, the time of the clock rising edge traveling in the delay circuit array 701 is equal to a time obtained by subtracting the delay time "d1" of the delay circuit 707 and the delay time "d2" of the delay circuit 708 from the clock period "tck", namely, {tck-d1-d2}.
Since the number of the delay circuit stages through which the rising edge of the low level pulse of the clock travels in the delay circuit array 702 is equal to the number of the delay circuit stages through which the rising edge of the clock traveled in the delay circuit array 701, the time in which the rising edge of the low level pulse of the clock travels in the delay circuit array 702 is equal to the time in which the rising edge of the clock travels in the delay circuit array 701, and therefore, is equal to a time obtained by subtracting the delay time "dl" of the delay circuit 707 and the delay time "d2" of the delay circuit 708 from the clock period "tck", namely, {tck-d1-d2}.
The time required for the clock to have passed through the amplifier circuit 706 is "d2" as mentioned above.
Thus, the time required for the clock to have passed through the receiver circuit 705, the delay circuit 707, the delay circuit 708, the delay circuit array 701, the delay circuit array 702, and the amplifier circuit 706, becomes "2tck", and therefore, the (m)th clock is outputted to the internal circuit 712 at the timing equal to that of the (m+2)th clock.
As mentioned above, an internal clock having no delay from the external clock can be obtained after two clocks.
When the prior art delay circuit device is used in the PLL circuit, a time (several ten periods or more) is required until the phase difference between the internal clock and the external clock becomes zero, and therefore, in order to obtain at a desired timing an internal clock having no phase difference from the external clock, it is necessary to maintain the PLL circuit in an operating condition, with the result that a current consumption is increased.
In addition, since the voltage controlled oscillator is so configured to control the oscillation by the voltage, if the power supply voltage lowers, the width of the control voltage correspondingly becomes small, with the result that the precision of the controlled frequency drops.
Therefore, in the case of controlling the frequency over a wide frequency range with a predetermined precision of the controlled frequency, it is a problem that it is necessary to provide a plurality of voltage controlled oscillators having different frequency ranges and a time is required until the phase difference becomes zero when the control voltage is changed.
The prior art delay circuit device shown in FIG. 7 was intended to overcome the above mentioned problems when it is used in the PLL circuit. Since the clock 803 outputted from the receiver circuit 705 is supplied to many NAND gates in the control circuit 703, it was a problem that a load capacitance to be driven is large, and the current consumption is large.
Namely, in order to ensure the operation when the clock period "tck" is long, it is necessary to increase the number of stages in the delay circuit 701, with the result that the load capacitance of the clock 802 correspondingly increases.